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hi-3282, hi-3282b arinc 429 serial transmitter and dual receiver general description the hi-3282 is a silicon gate cmos device for interfacing the arinc 429 serial data bus to a 16-bit parallel data bus. two receivers and an independent transmitter are provided. the receiver input circuitry and logic are designed to meet the arinc 429 specifications for loading, level detection, timing, and protocol. the arinc inputs of the hi-3282-10 configurations also have internal lightning protection to do-160d, level 3. the transmitter section provides the arinc 429 communication protocol. an external arinc 429 line driver such as the holt hi-3182 or hi-8585 is required to translate the 5 volt logic outputs to arinc 429 drive levels. the 16-bit parallel data bus exchanges the 32-bit arinc data word in two steps when either loading the transmitter or interrogating the receivers. the data bus interfaces with cmos and ttl. timing of all the circuitry begins with the master clock input, clk. for arinc 429 applications, the master clock frequency is 1 mhz. each independent receiver monitors the data stream with a sampling rate 10 times the data rate. the sampling rate is software selectable at either 1mhz or 125khz. the results of a parity check are available as the 32nd arinc bit. the transmitter has a first in, first out (fifo) memory to store 8 arinc words for transmission. the data rate of the transmitter is software selectable by dividing the master clock, clk, by either 10 or 80. the master clock is used to set the timing of the arinc transmission within the required resolution. the hi-3282bpjx product has a minimum low speed data rate of 6.5k bps. applications ? avionics data communication ? serial to parallel conversion ? parallel to serial conversion features ? arinc specification 429 compatible ? ? 16-bit parallel data bus ? direct receiver interface to arinc bus ? timing control 10 times the data rate ? selectable data clocks ? automatic transmitter data timing ? self test mode ? parity functions ? low power, single 5 volt supply ? industrial & extended temperature ranges compatible with industry-standard alternate parts ? small footprint 44-pin pqfp package option ? internal lightning protection of arinc inputs per do-160d, level 3 in -10 configurations 44-pin plastic quad flat pack (pqfp) july 2013 pin configuration (top view) 44 - n/c 43 - 429di2(b) 42 - 429di2(a) 41 - 429di1(b) 40 - 429di1(a) 39 - vcc 38 - 37 - 36 - txclk 35 - clk 34 - n/c dbcen mr 33 - n/c 32 - n/c 31 - x 30 - entx 29 - 28 -429do 27 - tx/r 26 - 25 - 24 - bd00 23 - bd01 cwstr 429do pl2 pl1 n/c-12 bd10 - 13 bd09 - 14 bd08 - 15 bd07 - 16 bd06 - 17 gnd-18 bd05 - 19 bd04 - 20 bd03 - 21 bd02 - 22 n/c - 1 -2 -3 sel - 4 -5 -6 bd15 - 7 bd14 - 8 bd13 - 9 bd12 - 10 bd11 - 11 d/r1 d/r2 en1 en2 hi-3282pqi hi-3282pqi-10 hi-3282pqt & hi-3282pqt-10 (see page 10 for additional pin configurations) (ds3282 rev. o) 07/13 holt integrated circuits www.holtic.com (
pin description hi-3282, hi-3282b symbol function description vcc power +5v 5% 429di1 (a) input arinc receiver 1 positive input 429di1 (b) input arinc receiver 1 negative input 429di2 (a) input arinc receiver 2 positive input 429di2 (b) input arinc receiver 2 negative input output receiver 1 data ready flag output receiver 2 data ready flag sel input receiver data byte selection (0 = byte 1) (1 = byte 2) input data bus control, enables receiver 1 data to outputs input data bus control, enables receiver 2 data to outputs if is high bd15 i/o data bus bd14 i/o data bus bd13 i/o data bus bd12 i/o data bus bd11 i/o data bus bd10 i/o data bus bd09 i/o data bus bd08 i/o data bus bd07 i/o data bus bd06 i/o data bus gnd power 0 v bd05 i/o data bus bd04 i/o data bus bd03 i/o data bus bd02 i/o data bus bd01 i/o data bus bd00 i/o data bus input latch enable for byte 1 entered from data bus to transmitter fifo. input latch enable for byte 2 entered from data bus to transmitter fifo. must follow tx/r output transmitter ready flag. goes low when arinc word loaded into fifo. goes high after transmission and fifo empty. 429do output "ones" data output from transmitter. output "zeroes" data output from transmitter. entx input enable transmission input clock for control word register clk input master clock input tx clk output transmitter clock equal to master clock (clk), divided by either 10 or 80. input master reset, active low input data bit control enable. (active low, with internal pull up to vdd). d/r1 d/r2 en1 en2 en1 pl1 pl2 pl1. 429do cwstr mr dbcen holt integrated circuits 2
arinc 429 data format the following table shows the bit positions in exchanging data with the receiver or the transmitter. arinc bit 1 is the first bit transmitted or received. data bd bd bd bd bd bd bd bd bd bd bd bd bd bd bd bd bus 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 arinc 13 12 11 10 9 31 30 32 12345678 bit byte 1 functional description data bus function control description pin bd04 paren enables parity bit insertion into transmitter data bit 32 if enabled, an internal connection bdo5 self test 0 = enable is made passing 429do and to the receiver logic inputs receiver 1 if enabled, arinc bits 9 and, bdo6 decoder 1 = enable 10 must match the next two control word bits if receiver 1 decoder is bdo7 - - enabled, the arinc bit 9 must match this bit if receiver 1 decoder is bdo8 - - enabled, the arinc bit 10 must match this bit receiver 2 if enabled, arinc bits 9 and bdo9 decoder 1 = enable 10 must match the next two control word bits if receiver 2 decoder is bd10 - - enabled, then arinc bit 9 must match this bit if receiver 2 decoder is bd11 - - enabled, then arinc bit 10 must match this bit invert logic 0 enables normal odd parity bd12 xmtr 1 = enable and logic 1 enables even parity parity output in transmitter 32nd bit bd13 xmtr data 0 = 10 clk is divided either by 10 or clk select 1 = 80 80 to obtain xmtr data clock bd14 rcvr dta 0 = 10 clk is divided either by 10 or clk select 1 = 80 80 to obtain rcvr data clock 429do control word register the hi-3282 contains 11 data flip flops whose d inputs are con- nected to the data bus and clocks connected to . each flip flop provides options to the user as follows: cwstr receivers arinc bus interface figure 1 shows the input circuit for each receiver. the arinc 429 specification requires the following detection levels: the hi-3282 guarantees recognition of these levels with a common mode voltage with respect to gnd less than 5v for the worst case condition (4.75v supply and 13v signal level). the tolerances in the design guarantee detection of the above levels, so the actual acceptance ranges are slightly larger. if the arinc signal is out of the actual acceptance ranges, including the nulls, the chip rejects the data. state differential voltage one +6.5 volts to +13 volts null +2.5 volts to -2.5 volts zero -6.5 volts to -13 volts receiver logic operation figure 2 shows a block diagram of the logic section of each receiver. byte 2 data bd bd bd bd bd bd bd bd bd bd bd bd bd bd bd bd bus 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 arinc 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 bit hi-3282, hi-3282b v cc v cc gnd gnd 429di1 (b) 429di2 (b) or 429di1 (a) 429di2 (a) or differential amplifiers ones comparators null zeroes figure 1. arinc receiver input holt integrated circuits 3
bit timing the arinc 429 specification contains the following timing specification for the received data: 100k bps 1% 12k -14.5k bps (hi-3282bpjx-xx only - 6.5k bps min.) 1.5 0.5 sec 10 5 sec 1.5 0.5 sec 10 5 sec 5 sec 5% 34.5 to 41.7 sec high speed low speed bit rate pulse rise time pulse fall time pulse width (hi-3282bpjx-xx only - 76.9 sec max.) the 32nd bit of received arinc words stored in the receive fifo is used as a parity flag indicating whether good odd parity is re- ceived from the incoming arinc word. the parity bit is reset to indicate correct parity was received and the resulting word is then written to the receive fifo. the receiver sets the 32nd bit to a ?1?, indicating a parity error and the resulting word is then written to the receive fifo. therefore, the 32nd bit retrieved from the receiver fifo will always be a ?0? when valid (odd parity) arinc 429 words are received. once 32 valid bits are recognized, the receiver logic generates an end of sequence (eos). if the receiver decoder is enabled and the 9th and 10th arinc bits match the control word program bits or if the receiver decoder is disabled, then the eos clocks the receiver parity odd parity received even parity received retrieving data functional description (cont.) sel en d/r decoder control bits / mux control latch enable control 32 to 16 driver 32 bit latch 32 bit shift register to pins control bit bd14 clock option clock clk bit counter and end of sequence parity check 32nd bit data bit clock eos word gap word gap timer bit clock end start sequence control error clock error detection shift register shift register null zeros shift register ones eos bits9&10 figure 2. receiver block diagram hi-3282, hi-3282b data ready flag flip flop to a "1", or (or both) will go low. the data flag for a receiver will remain low until after arinc bytes from that receiver are retrieved. this is accomplished by activating with sel, the byte selector, low to retrieve the first byte and activating with sel high to retrieve the second byte. retrieves data from receiver 1 and retrieves data from receiver 2. if another arinc word is received and a new eos occurs before the two bytes are retrieved, the data is overwritten by the new word. d/r1 d/r2 en en en1 en2 both internal lightning protection (-10 only) application note 300 the hi-3282-10 configurations are similar to the hi-3282 with the exception that it allows an external 10k to 15k ohm resistor to be added in series with each arinc input without affecting the arinc input thresholds. this option is especially useful in applications where lightning protection circuitry is also required. the design of the hi-3282-10 device requires the external 10k to 15k ohm series resistors for proper arinc level detection. the typical 10 volt differential signal is translated and input to a window comparator and latch. the comparator levels are set so that, with the external 10k to 15k ohm resistors, they are just below the standard 6.5 v minimum arinc data threshold and just above the 2.5 v maximum arinc null threshold. the receivers of the hi-3282-10 when used with external 15k ohm resistors will withstand do-160f, level 3, waveforms 3, 4, 5a and 5b. no additional lightning protection circuit is necessary. please refer to the holt an-300 application note for additional information and recommendations on lightning protection of holt line drivers and receivers. holt integrated circuits 4
control register bit bd13 figure 3. transmitter block diagram data clock pl1 pl2 clk tx clk parity generator data and null timer sequencer bit and word gap counter start sequence word counter and fifo control increment word count data clock divider fifo loading sequencer 429do 429do 8 x 31 fifo 31 bit parallel load shift register bit clock word clock address load data bus tx/r entx control register bd04, bd12 dbcen functional description (cont.) transmitter a block diagram of the transmitter section is shown in figure 3. the fifo is loaded sequentially by first pulsing to load byte 1 and then to load byte 2. the control logic automatically loads the 31 bit word in the next available position of the fifo. if tx/r, the transmitter ready flag, is high (fifo empty), then 8 words, each 31 bits long, may be loaded. if tx/r is low, then only the available positions may be loaded. if all 8 positions are full, the fifo ignores further attempts to load data. when entx goes high, enabling transmission, the fifo positions are incremented with the top register loading into the data transmission shift register. within 2.5 data clocks the first data bit appears at either 429do or . the 31 bits in the data transmission shift register are presented sequentially to the outputs in the arinc 429 format with the following timing: arinc data bit time 10 clocks 80 clocks data bit time 5 clocks 40 clocks null bit time 5 clocks 40 clocks word gap time 40 clocks 320 clocks the word counter detects when all loaded positions are transmitted and sets the transmitter ready flag, tx/r, high. fifo operation data transmission pl1 pl2 429do high speed low speed transmitter parity control register bit bd04 (paren) enables parity bit insertion into transmitter data bit 32. parity is always inserted if dbcen is open or high. if dbcen is low, logic 0 on paren inserts data on bit 32, and logic 1 on paren inserts parity on bit 32. hi-3282, hi-3282b the parity generator counts the ones in the 31-bit word. if the bd12 control word bit is set low, the 32nd bit transmitted will make parity odd. if the control bit is high, the parity is even. if the bd05 control word bit is set low, 429do or are internally connected to the receivers inputs, bypassing the interface circuitry. data to receiver 1 is as transmitted and data to recevier 2 is the complement. 429do and outputs remain active during self test. the two receivers are independent of the transmitter. therefore, control of data exchanges is strictly at the option of the user. the only restrictions are: 1. the received data may be overwritten if not retrieved within one arinc word cycle. 2. the fifo can store 8 words maximum and ignores attempts to load addition data if full. 3. byte 1 of the transmitter data must be loaded first. 4. either byte of the received data may be retrieved first. both bytes must be retrieved to clear the data ready flag. 5. after entx, transmission enable, goes high it cannot go low until tx/r, transmitter ready flag, goes high. otherwise, one arinc word is lost during transmission. self test system operation 429do 429do master reset ( ) mr on a master reset data transmission and reception are immedi- ately terminated, the transmit fifo and receivers cleared as are the transmit and receive flags. the control register is not affected by a master reset. holt integrated circuits 5
repeater operation the repeater mode of operation allows a data word that has been received by the hi-3282 to be placed directly into its fifo for transmission. after a 32-bit word has been shifted into the receiver shift register, the flag will go low. a logic "0" is placed on the sel line and is strobed. this is the same procedure as for normal receiver operation and it places the lower byte (16) of the data word on the data bus. by strobing at the same time as d/r en pl1 en, the byte functional description (cont.) will also be placed into the transmitter fifo. sel is then taken high and is strobed again to place the upper byte of the data word on the data bus. by strobing at the same time as , the second byte will also be placed into the fifo. the data word is now ready to be transmitted according to the parity programmed into the control word register. in normal operation, either byte of a received data word may be read from the receiver latches first by use of sel input. during repeater operation however, the lower byte of the data word must be read first. this is necessary because, as the data is being read, it is also being loaded into the fifo and the transmitter fifo is always loaded with the lower byte of the data word first. en pl2 en receiver operaton data ready flag d/r arinc data byte select sel enable byte on bus en data bus bit 31 bit 32 selen t d/r t ensel t dataen t d/ren t end/r t en t ensel t selen t dataen t endata t endata t enen t don't care don't care don't care byte 1 valid byte 2 valid loading control word cwhld t cwset t cwstr t data bus cwstr valid data rate - example pattern 429do 429do arinc bit null data data data null null word gap bit 1 next word bit 32 bit 31 bit 30 timing diagrams hi-3282, hi-3282b holt integrated circuits 6
timing diagrams (cont.) repeater operation timing don't care 429di d/r en pl1 pl2 sel tx/r entx 429do bit 32 don't care d/r t en t d/ren t enen t en t end/r t selen t ensel t enpl t plen t selen t ensel t enpl t plen t tx/r t tx/ren t endat t entx/r t dtx/r t null t bit 1 bit 32 transmitting data arinc bit 429do or 429do pl2 entx tx/r pl2en t endat t dtx/r t entx/r t data bit 1 data bit 2 data bit 32 transmitter operation pl2 dwset t dwhld t tx/r t dwhld t pl12 t pl t data bus pl1 tx/r byte 2 valid pl t pl12 t dwset t byte 1 valid hi-3282, hi-3282b holt integrated circuits 7
limits parameter conditions unit symbol differential input voltage: one v common 6.5 10.0 13.0 v zero v mode voltage less than 5v -13.0 -10.0 -6.5 v null v with respect to gnd -2.5 0 2.5 v input resistance: differential r includes the external 10k 12 k to gnd r resistors in series with each arinc 12 27 k to vcc r input of a -10 configuration 12 27 k input current: input sink i 200 a input source i -450 a input capacitance: differential c 20 pf (guaranteed but not tested) to gnd c 20 pf to vcc c 20 pf input voltage: input voltage hi v 2.0 v input voltage lo v 0.8 v input current: input sink i 1.5 a input source i -1.5 a input voltage: input voltage hi v 2.0 v input voltage lo v 0.8 v input current: input sink i 10 a input source i -10 a pull-up current ( pin) i -150 -50 a output voltage: logic "1" output voltage v i = -1.5ma 2.7 v logic "0" output voltage v i = 1.6ma 0.4 v output current: output sink i v = 0.4v 1.6 ma (bi-directional pins) output source i v = v - 0.4v -1.0 ma output current: output sink i v = 0.4v 1.6 ma (all other outputs) output source i v = v - 0.4v -1.0 ma output capacitance: c 15 pf standby supply current: i 10 ma operating supply current: i 10 ma min typ max arinc inputs - pins: 429di1(a), 429di1(b), 429di2(a), 429di2(b) bi-directional inputs - pins:bd00-bd15 all other inputs outputs supply input ih il nul i g h ih il i g h ih il ih il ih il ih il pu oh oh ol ol ol out oh out cc ol out oh out cc o cc1 cc2 dcben power dissipation 500mw operating temperature range: (industrial) -40c to +85c (extended) -55c to +125c storage temperature range: -65c to +150c absolute maximum ratings supply voltage vcc -0.3v to +7v voltage at arinc input pins -120v to +120v voltage at any other pin -0.3v to vcc +0.3v dc current drain per input pin 10ma note: stresses above those listed under "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not imp lied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings dc electrical characteristics hi-3282, hi-3282b vcc = 5v 5%, gnd = 0v, ta = operating temperature range (unless otherwise specified). holt integrated circuits 8
limits parameter symbol units min typ max pulse width - t 50 ns setup - data bus valid to high t 50 ns hold - high to data bus hi-z t 0 ns delay - start arinc 32nd bit to low: high speed t 16 s low speed t 128 s delay - low to l0w t 0 ns delay - low to high t 200 ns setup - sel to l0w t 10 ns hold - sel to high t 10 ns delay - l0w to data bus valid t 50 80 ns delay - high to data bus hi-z t 30 ns pulse width - or t 80 ns spacing - high to next l0w t 50 ns pulse width - or t 50 ns setup - data bus valid to high t 50 ns hold - high to data bus hi-z t 10 ns spacing - or t 0 ns delay - high to tx/r low t 840 ns spacing - high to entx high t 0 s delay - entx high to 429do or : high speed t 25 s delay - entx high to 429do or : low speed t 200 s delay - 32nd arinc bit to tx/r high t 50 ns spacing - tx/r high to entx l0w t 0 ns delay - low to low t 0 ns hold - high to high t 0 ns delay - tx/r low to entx high t 0 ns t50 ns 1% control word timing receiver timing fifo timing transmission timing repeater operation timing master reset pulse width arinc data rate and bit timing cwstr cwstr cwstr d/r d/r en en d/r en en en en en1 en2 en en pl1 pl2 pl pl pl1 pl2 pl2 pl2 429d0 429d0 en pl pl en cwstr cwset cwhld d/r d/r d/ren end/r selen ensel endata dataen en enen pl dwset dwhld pl12 tx/r pl2en endat endat dtx/r entx/r enpl plen tx/ren mr ac electrical characteristics vcc = 5v, gnd = 0v, ta = operating temperature range and fclk = 1mhz 0.1% with 60/40 duty cycle + hi-3282, hi-3282b holt integrated circuits 9
pin configuration (top view) hi-3282cdi / hi-3282cdt / hi-3282cdm 40-pin ceramic side-brazed dip hi-3282cdi-10 / hi-3282cdt-10 / hi-3282cdm-10 dbcen mr master reset cwstr control word strobe 429do xmit data pl2 xmit byte 2 le pl1 xmit byte 1 le () tx clk (xmit clock out) clk (master clk in) nc nc () entx (enable xmit) () 429do (xmit data) tx/r (xmit ready flag) () () bd00 bd01 bd02 bd03 bd04 bd05 gnd 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 vcc (rec. 1 input) 429di1(a) (rec.1 input) 429di1(b) (rec. 2 input) 429di2(a) (rec. 2 input) 429di2(b) () () (rec. byte select) sel () () bd15 bd14 bd13 bd12 bd11 bd10 bd09 bd08 bd07 bd06 rec.1 data flag d/r1 rec.2 data flag d/r2 rec. 1 output enable en1 rec. 2 output enable en2 n/c 7 8 9 sel 10 11 12 bd15 13 bd14 14 bd13 15 bd12 16 bd11 17 d/r1 d/r2 en1 en2 39 n/c 38 n/c 37 36 entx 35 34 429do 33 tx/r 32 31 30 bd00 29 bd01 cwstr 429do pl2 pl1 n/c 18 bd10 19 bd09 20 bd08 21 bd07 22 bd06 23 gnd 24 bd05 25 bd04 26 bd03 27 bd02 28 6 n/c 5 429di2(b) 4 429di2(a) 3 429di1(b) 2 429di1(a) 1 vcc 44 43 42 tx clk 41 clk 40 n/c dbcen mr hi-3282pji / hi-3282bpji hi-3282pjt / hi-3282bpjt hi-3282pji-10 / hi-3282bpji-10 hi-3282pjt-10 / hi-3282bpjt-10 44-pin j-lead plcc hi-3282cli / hi-3282ct / hi-3282clm 44-pin leadless chip carrier (lcc) hi-3282cli-10 / hi-3282ct-10 / hi-3282clm-10 dbcen hi-3282, hi-3282b additional hi-3282 pin configurations (see page 1 for the 44-pin plastic qfp) holt integrated circuits 10
ordering information hi - 3282 (ceramic) cx x -xx hi - 3282 (plastic) xpxxx-xx hi-3282, hi-3282b part package number description pj 44 pin plastic j-lead plcc (44j) pq 44 pin plastic quad flat pack (44pqs) part temperature burn number range flow in i -40c to +85c i no t -55c to +125c t no m -55c to +125c m yes part package number description blank tin / lead (sn / pb) solder f 100% matte tin (pb-free rohs compliant) no dash number 35k ohm 0 -10 (see note 1) 25k ohm 10k to 15k ohm part input series resistance number built-in required externally part package number description cd 40 pin ceramic side brazed dip (40c) cl 44 pin ceramic leadless chip carrier (44s) part temperature burn lead number range flow in finish i -40c to +85c i no gold (pb-free, rohs compliant) t -55c to +125c t no gold (pb-free, rohs compliant) m -55c to +125c m yes tin / lead (sn / pb) solder no dash number 35k ohm 0 -10 (see note 1) 25k ohm 10k to 15k ohm part input series resistance number built-in required externally notes: 1. the -10 configuration requires an external 10k to 15k ohm resistor in series with each arinc input to guarantee specified voltage thresholds. the 15k ohm resistors are required to withstand do-160f, level 3, waveforms 3 ,4,5a&5bpin injection. part minimum number low speed data rate blank 10.4 k bps b 6.5k bps (pj package only) holt integrated circuits 11
revision history p/n rev. date description of change ds3282 l 02/24/09 clarified the temperature ranges, series resistance values for ?-10? devices, and note (1) in the ordering information. m 12/21/10 added hi-3282bpjx standard product with minimum low speed receive data rate of 6.5k bps n 05/21/12 change tselen and tensel in ac characteristics table from 0ns to 10ns. update pqfp package drawing to 44pmqs o 07/30/13 updated receiver parity and pqfp package information. update voltage at arinc input pins from +/-29v to +/-120v hi-3282, hi-3282b holt integrated circuits 12
hi-3282, hi-3282b package dimensions inches (millimeters) package type: 40c 40-pin ceramic side-brazed dip bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95) 2.020 max (51.308 max) .225 max (5.715 max) .018 typ (.457 typ) .050 typ (1.270 typ) .085 .009 (2.159 .229) .125 min (3.175 min) .610 .010 (15.494 .254) .600 .010 (15.240 .254) .595 .010 (15.113 .254) .010 .002 .001 (.254 .051 .025) .100 (2.54) bsc 44-pin plastic plcc inches (millimeters) package type: 44j bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95) pin no. 1 ident .045 x 45 .045 x 45 pin no. 1 .173 .008 (4.394 .203) .690 .005 (17.526 .127) sq. .610 .020 (15.494 .508) .031 .005 (.787 .127) .653 .004 (16.586 .102) sq. .017 .004 (.432 .102) .050 (1.27) bsc detail a r .010 .001 (.254 .03) .020 (.508) min see detail a .035 .010 (.889 .254) holt integrated circuits 13
hi-3282 package dimensions 44-pin ceramic leadless chip carrier inches (millimeters) package type: 44s .651 .011 (16.535 .279) sq. .075 .004 (1.905 .101) .326 .006 (8.280 .152) pin 1 .050 (1.270) .009r .006 (.229r .152) .092 028 (2.336 .711) .025 .003 (.635 .076) .050 005 (1.270 .127) pin 1 bsc .020 (.508) index .040 x 45 (1.016 x 45) 3 plcs bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95) package type: 0 7 detail a see detail a sq. 44pmqs 44-pin plastic quad flat pack (pqfp) .009 (.23) .520 .010 (13.20 .25) .394 .004 (10.0 .10) sq. max. .014 .003 (.37 .08) .035 .006 (.88 .15) .005 (.13) r min. .012 (.30) r max. .079 .008 (2.0 .20) .096 (2.45) max. .0315 (.80) inches (millimeters) bsc bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95) holt integrated circuits 14

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